Integrated chips are made by a process that comprises a design step and a subsequent fabrication step. During the design step, a layout of an integrated chip is generated as an electronic file. The layout comprises geometric shapes corresponding to structures to be fabricated on-chip. During the fabrication step, the layout is formed onto a semiconductor workpiece.
The resolution that a conventional lithography tool can achieve is limited to about a 45 nanometer (nm) half pitch. To continue to use existing lithography tools to resolve smaller spaces, double exposure methods have been developed. Double exposure involves breaking up the geometric shapes of a layout in a manner that forms patterns on a single layer of a substrate using multiple different masks in succession. By breaking a layout into multiple different masks, a minimum line spacing in the combined pattern is reduced while maintaining good resolution. A number of different multiple exposure techniques have been developed. In double dipole lithography (DDL), the patterns to be formed on a layer are decomposed and formed on a first mask having only horizontal lines, and on a second mask having only vertical lines. Double patterning technology (DPT) allows a vertex (angle) to be formed of a vertical segment and a horizontal segment on a same mask.